Qualification

Bachelor or Grasp’s diploma in Electronics engineering.

3+ years of design expertise

Expertise with Chip degree DFT and Submit Silicon debug / evaluation

Understanding of DFT architectures like JTAG, Scan Compression Methods, scan chain insertion and verification.

Should have expertise producing scan patterns and protection statistics for varied fault fashions like caught at, IDDQ, Transition faults, JTAG BSDL, sample technology for Recollections(E-fuse and so forth.). Expertise debugging tester failures of scan patterns, prognosis and sample re-generation.

Design expertise in MBIST / LBIST is an added benefit.

Good understanding of constraints growth for Bodily Design Implementation / Static Timing Evaluation.

Most well-liked Expertise/Expertise

  • Expertise with TCL /Perl is most popular.
  • Efficient communication expertise to work together with cross-functional groups.
  • Take part 15 days

Location: Hyderabad/Noida/Bangalore

Firm: Tecquire Options Pvt Ltd