Rambus, a premier chip and silicon IP supplier, is searching for to rent an distinctive Senior Member Technical Workers for our IP cores staff in Bangalore. Candidates will likely be becoming a member of a few of the brightest inventors and engineers on this planet to develop merchandise that make knowledge quicker and safer.
The candidate will likely be reporting to Selvakumar, Supervisor Design implementation and is a Fulltime place. The candidate may have the next publicity to the administration and he/she will likely be a part of main technical choice making. The design requires out of field considering to fulfill tighter PPA.
- Lead full possession of IP cores PHY and Testchip implementation.
- Take full possession for Block and SOC implementation relying on the complexity.
- Chargeable for impartial planning and execution of all points of bodily design together with synthesis, ground planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Energy and Sign Integrity Evaluation, Bodily Verification, DFM and Tape Out on 7nm nodes or beneath.
- Will need to have participated in all levels of the design. (ground planning, placement, CTS, routing, crosstalk avoidance, bodily verification, IREM)
- Nicely versed with IP improvement and integration course of at testchip or SOC stage
- Nicely versed with the timing closure (STA), timing closure methodologies.
- Ought to be capable of present clear instructions to the staff on PnR flows.
- Function includes duties in estimating energy utilizing trade commonplace device , designing energy grid , analyze energy grid, doing static IR drop, dynamic IR drop
- Function includes analyzing DRC, LVS,ERC and PERC rule recordsdata for trade commonplace format verification
- Good communication ability to barter with high stage for convergence.
- Work intently with Undertaking chief for creating schedule, monitoring and elevating points / dangers to undertaking administration.
- Take part in Mentoring new joiners within the group on technical abilities.
- Present inputs for CAD/DA staff from Design Implementation perspective.
- Work intently with DFT staff on scan points and supply inputs from bodily design.
- Constantly work on methodology and productiveness enhancements.
- Will need to have minimal Bachelors diploma in EE/ECE (diploma’s associated to electronics) from a reputed institute.
- Will need to have not less than expertise within the vary of three to five yrs in bodily design
- Will need to have applied and accomplished a minimal of 5 design tapeouts.
- Will need to have detailed data of EDA instruments and flows, Cadence associated basis flows and RTL2GDS circulate is desired
- Expertise in Tcl/Tk, PERL is a Plus
- Synthesis expertise and publicity moreover chip implementation flows is an added benefit